Since the dawning of the digital computing era, clock generation systems have continuously evolved. Examples of such clock generation systems include: high-speed, multiphased clocking systems for efficient computing engines, non-overlapping control clocks for time critical operations, stable high-speed clocks for communication systems, and multiple duty cycle system clock generators for pulse width modulation and control applications. It should be understood that a duty cycle is calculated as a high time of the system clock divided by a period of the system clock. As a result of the introduction of mixed signal data processing systems, clock generation system requirements continue to increase in complexity. For example, modern mixed-signal data processing integrated circuit chips (known as "micro controllers") include a versatile composite of digital and analog subsystems which are required to coexist and to utilize a common system clock. The coexistence of the digital and analog subsystems mandates the growth of distinctly different clocking schemes within a common integrated environment.
Since each of these individual analog and digital subsystems functions within its own operating parameters, each may require a clock distinctly different from the main system clock. For example, Motorola's MCHC16Z1 analog-to-digital converter (A/D) module utilizes a user programmable prescaled system clock to produce a 50% duty cycle clock for usage by the A/D converter module. It is a unique and useful implementation for deriving an A/D converter clock from a much higher system clock frequency. By prescaling the system clock with a 5 bit modulus counter and passing it through an additional fixed divide by 2 circuit, a 50% duty cycle clock is always generated for usage by the A/D converter module. However, aside from defining operational boundary conditions conveniently, a fixed 50% duty cycle may not optimize either an analog or digital subsystem's performance.
Another distinctly different application in which a system clock on a microcontroller is modified specifically for usage by an internal subsystem is a variable duty cycle clock generator. Variable duty cycle clock generators or pulse width modulation circuits are popular for control of external time critical events.
In a data processing system component, such as an analog to digital converter, a first operation occurring on a first clock phase may require a different execution time than a second operation occurring on a second clock phase. In such a component, performance of the data processing system is limited by the existence of a fixed duty cycle clock because the frequency and duty cycle provided to the component must accomodate the slowest operation executed by that component. Therefore, a need exists for a method for modifying the clock frequency and duty cycle to reflect the operations currently executed by the component.